agilent hsmp-381x, 481x surface mount rf pin low distortion attenuator diodes data sheet features diodes optimized for: low distortion attenuating microwave frequency operation surface mount packages single and dual versions tape and reel options available low failure in time (fit) rate [1] lead-free option available note: 1. for more information see the surface mount pin reliability data sheet. package lead code identification, sot-23 (top view) description/applications the hsmp-381x series is specifically designed for low distortion attenuator applica- tions. the hsmp-481x products feature ultra low parasitic inductance in the sot-23 and sot-323 packages. they are specifically designed for use at frequencies which are much higher than the upper limit for conventional diodes. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime. common cathode #4 common anode #3 series #2 single #0 12 3 12 3 12 3 12 3 4810 12 3 dual cathode package lead code identification, sot-323 (top view) common cathode f common anode e series c single b 481b dual cathode
2 absolute maximum ratings [1] t c = +25 c symbol parameter unit sot-23 sot-323 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v same as v br same as v br t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25 c, where t c is defined to be the temperature at the package pins where contact is made to the circuit board. electrical specifications t c = +25 c (each diode) conventional diodes minimum maximum maximum minimum maximum part package breakdown total total high low number marking lead voltage resistance capacitance resistance resistance hsmp- code code configuration v br (v) r t ( ? )c t (pf) r h ( ? )r l ( ? ) 3810 e0 0 single 100 3.0 0.35 1500 10 3812 e2 2 series 3813 e3 3 common anode 3814 e4 4 common cathode 381b e0 b single 381c e2 c series 381e e3 e common anode 381f e4 f common cathode test conditions v r = v br i f = 100 ma v r = 50 v i r = 0.01 ma i f = 20 ma measure f = 100 mhz f = 1 mhz f = 100 mhz f= 100 mhz i r 10 a high frequency (low inductance, 500 mhz 3 ghz) pin diodes minimum maximum typical maximum typical part package breakdown series total total total number marking lead voltage resistance capacitance capacitance inductance hsmp- code code configuration v br (v) r s ( ? )c t (pf) c t (pf) l t (nh) 4810 eb b dual cathode 100 3.0 0.35 0.4 1.0 481b eb b dual cathode test conditions v r = v br i f = 100 ma v r = 50 v v r = 50 v f = 500 mhz measure f = 1 mhz f = 1 mhz 3 ghz i r 10 av r = 0 v
3 typical parameters at t c = 25 c part number series resistance carrier lifetime reverse recovery time total capacitance hsmp- r s ( ? ) (ns) t rr (ns) c t (pf) 381x 75 1500 300 0.27 @ 50 v test conditions i f = 1 ma i f = 50 ma v r = 10 v f = 1 mhz f = 100 mhz i r = 250 ma i f = 20 ma 90% recovery typical parameters at t c = 25 c (unless otherwise noted), single diode 10000 1000 100 10 1 rf resistance (ohms) 0.01 0.1 1 10 100 i f ?forward bias current (ma) t a = +85 c t a = +25 c t a = 55 c figure 2. rf resistance vs. forward bias current. 0.15 0.30 0.25 0.20 0.35 0.40 0.45 02 6 41012 816 14 18 20 total capacitance (pf) reverse voltage (v) figure 1. rf capacitance vs. reverse bias. 1 mhz 30 mhz frequency>100 mhz 120 110 100 90 80 70 60 50 40 1000 100 10 diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz diode rf resistance (ohms) figure 3. 2nd harmonic input intercept point vs. diode rf resistance. input intercept point (dbm) 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f ?forward current (ma) v f ?forward voltage (ma) figure 4. forward current vs. forward voltage. 125 c 25 c ?0 c input rf in/out figure 5. four diode attenuator. see application note 1048 for details. fixed bias voltage variable bias typical applications for multiple diode products
4 typical applications for hsmp-481x low inductance series microstrip series connection for hsmp-481x series in order to take full advantage of the low inductance of the hsmp-481x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in figure 7. figure 7. circuit layout. 0.3 nh 0.3 nh 0.3 pf r j 1.5 nh 1.5 nh figure 9. equivalent circuit. r j 0.08 + 2.5 i b 0.9 12 3 figure 6. internal connections. hsmp-481x microstrip shunt connections for hsmp-481x series in figure 8, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the hsmp-481x series diode are placed across the resulting gap. this forces the 1.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. the 0.3 nhof shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 50 ohm microstrip lines pad connected to ground by two via holes figure 8. circuit layout.
5 typical applications for hsmp-481x low inductance series (continued) figure 10. circuit layout. co-planar waveguide groundplane center conductor groundplane co-planar waveguide shunt connection for hsmp-481x series co-planar waveguide, with ground on the top side of the printed circuit board, is shown in figure 10. since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. figure 11. equivalent circuit. 0.3 pf 0.75 nh r j 0.18 pf* * measured at -20 v 2.5 ? r j r s c j r j = 80 ? i 0.9 r t = 2.5 + r j c t = c p + c j i = forward bias current in ma *see an1124 for package models. equivalent circuit model hsms-381x chip*
6 assembly information sot-323 pcb footprint a recommended pcb pad layout for the miniature sot-323 (sc-70) package is shown in figure 12 (dimensions are in inches). this layout provides ample allowance for package placement by auto- mated assembly equipment without adding parasitics that could impair the performance. 0.026 0.039 0.079 0.022 dimensions in inches figure 12. recommended pcb pad layout for agilent s sc70 3l/sot-323 products. sot-23 pcb footprint 0.039 1 0.039 1 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 figure 13. recommended pcb pad layout for agilent s sot-23 products. time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 14. surface mount assembly profile. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. agilent s diodes have been qualified to the time-temperature profile shown in figure 14. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporat- ing solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 235 c. these parameters are typical for a surface mount assembly process for agilent diodes. as a general guideline, the circuit board and components should be exposed only to the minimum tempera- tures and times necessary to achieve a uniform reflow of solder.
7 package dimensions outline sot-323 (sc-70) package characteristics lead material ................................... copper (sot-323); alloy 42 (sot-23) lead finish ................................... tin-lead 85-15% (non lead-free option) or tin 100% (lead-free option) maximum soldering temperature .............................. 260 c for 5 seconds minimum lead strength .......................................................... 2 pounds pull typical package inductance .................................................................. 2 nh typical package capacitance .............................. 0.08 pf (opposite leads) outline 23 (sot-23) ordering information specify part number followed by option. for example: h smp - 381x - xxx bulk or tape and reel option part number; x = lead code surface mount pin option descriptions -blk = bulk, 100 pcs. per antistatic bag -tr1 = tape and reel, 3000 devices per 7" reel -tr2 = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. for lead-free option, the part number will have the character "g" at the end, eg. -tr2g for a 10k pc lead-free reel. e b e2 e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.79 0.000 0.37 0.086 2.73 1.15 0.89 1.78 0.45 2.10 0.45 max. 1.20 0.100 0.54 0.152 3.13 1.50 1.02 2.04 0.60 2.70 0.69 symbol a a1 b c d e1 e e1 e2 e l e b e1 e1 c e xxx l d a a1 notes: xxx-package marking drawin g s are not to scale dimensions (mm) min. 0.80 0.00 0.15 0.10 1.80 1.10 1.80 max. 1.00 0.10 0.40 0.20 2.25 1.40 2.40 symbol a a1 b c d e1 e e1 e l 1.30 typical 0.65 typical 0.425 typical
8 tape dimensions and product orientation for outline sot-23 note: "ab" represents package marking code. "c" represents date code. end vie w 8 mm 4 mm top view abc abc abc abc device orientation for outlines sot-23/323 user feed direction cover tape carrier tape reel 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0.05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 ? 0.10 0.229 0.013 0.315 + 0.012 ? 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (65) 6755 2044 taiwan: (65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. obsoletes 5989-2497en september 2 8 , 2005 5989-4025en p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8 c max for sot-363 (sc70-6 lead) 10 c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape tape dimensions and product orientation for outline sot-323
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